1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to an input/output data pipeline circuit of a semiconductor memory device and the semiconductor memory device.
2. Description
During the read operation of a semiconductor memory device, data stored in a memory cell is output to a data output driver by predetermined read address signals. A semiconductor memory device is capable of performing a burst operation, in which a plurality of data is continuously output. Such a semiconductor memory device includes a pipeline circuit, located between the data output driver and a memory cell array.
FIG. 1 is a circuit diagram of an input/output data pipeline circuit of a conventional semiconductor memory device. An input/output data pipeline circuit 1000 of FIG. 1 includes a first pipeline circuit 100 and a data output circuit 110. The first pipeline circuit 100 includes a first switching circuit 11, a latching circuit 12, and a second switching circuit 13.
In response to activation of the first switching signal WRTPIPE, the first switching circuit 11 is switched on and outputs data RWD read from a memory cell. The latching circuit 12 receives and latches the output of the first switching circuit 11, and outputs an inverted signal of the output of the first switching circuit 11. In response to activation of the second switching signal LOAD, the second switching circuit 13 is switched on and outputs the signal from the latching circuit 12. Based on the logic state and time delay of the data RWD, an inverter 14 may be connected to the output terminal of the second switching circuit 13.
The data output circuit 110 includes an inverter 15 and a third switching circuit 16. The data output circuit 110 is connected to the output of an nth pipeline circuit (not shown) and outputs the output signal OUTN of the nth pipeline circuit (not shown) in response to activation of the selection signal SEL. Output signal OUTN of the nth pipeline circuit (not shown) is identical to output signal OUT of the first pipeline circuit 100, and is output after the nth pipeline circuit (not shown) receives data from another memory cell.
Data output to a data output driver (not shown) is selected based on logic states of the selection signal SEL, the first switching signal WRTPIPE, and the second switching signal LOAD. For example, when selection signal SEL is inactive, and first switching signal WRTPIPE and second switching signal LOAD are active, output signal OUT of the first pipeline circuit 100 is output to the data output driver (not shown).
When selection signal SEL, first switching signal WRTPIPE, and second switching signal LOAD are active, output signal OUTN of the nth pipeline circuit (not shown) is output to the data output driver (not shown).
Data RWD, read from the memory cell, is processed and output by the first pipeline circuit 100. Namely, data RWD is output through the first switching circuit 11 that is switched on in response to activation of the first switching signal WRTPIPE and inverted signal WRTPIPEB thereof, latched by the latching circuit 12, and then output through the second switching circuit 13 that is switched on in response to activation of the second switching signal LOAD and inverted signal LOADB thereof.
To output data RWD without distortion, the second switching signal LOAD is activated after the first switching signal WRTPIPE is activated. In other words, when first switching signal WRTPIPE is activated to logic high, data RWD is transmitted to the latching circuit 12, and the latching circuit 12 latches and outputs data RWD. Once the second switching signal LOAD is activated, data RWD passes through the second switching unit 13 without distortion.
However, if the frequency of the clock signal becomes higher or data RWD is input to the first pipeline circuit 100 too late, the second switching signal LOAD may activate prior to activation of the first switching signal WRTPIPE. If this occurs, the window of data RWD may be small and erroneous data may be fed to the first pipeline circuit 100.
Accordingly, there exists the need for a pipeline circuit that can determine whether the second switching signal LOAD is activated prior to activation of the first switching signal WRTPIPE and output data without distortion based on the determined result.
The present invention provides an input/output data pipeline circuit which generates a control signal based on a clock signal of a semiconductor memory device and is controlled by the logic state of the control signal.
The present invention also provides a semiconductor memory device with the input/output data pipeline circuit.
According to an aspect of the present invention, there is provided an input/output data pipeline circuit of a semiconductor memory device. The input/output data pipeline circuit comprises a first transmitting unit, a control signal generating unit, and a second transmitting unit. The first transmitting unit receives data stored in a memory cell and transmits data to an input/output driver in response to activation of a first switching signal and a second switching signal. The control signal generating unit receives a clock signal from the semiconductor memory device and, corresponding to the frequency of the clock signal, outputs a control signal, the first switching signal, and the second switching signal. The second transmitting unit transmits data to the input/output driver in response to activation of the control signal. The first transmitting unit and the second transmitting unit are alternatively activated.
Preferably, the first transmitting unit comprises a first switching circuit, which outputs data in response to activation of the first switching signal, a latching circuit, which latches and outputs the output of the first switching circuit, and a second switching circuit, which outputs the output of the latching circuit to the input/output driver in response to activation of the second switching signal.
Preferably, the second transmitting unit comprises a third switching circuit, which outputs data to the input/output driver in response to activation of the control signal.
According to another aspect of the present invention, there is provided a semiconductor memory device. The semiconductor memory device comprises a memory cell core, an input/output driver, an input/output data pipeline circuit, and a control signal generating unit. The memory cell core includes a plurality of memory cells. The input/output driver receives first data from outside of the semiconductor memory device, in synchronization with a first clock signal, or outputs second data stored in the memory cell core, in synchronization with a second clock signal. The input/output data pipeline circuit is connected to the memory cell core and the input/output driver, and transmits the second data stored in the memory cell core to the input/output driver or transmits the first data received from outside of the semiconductor memory device to the memory cell core. The control signal generating unit receives the first clock signal and the second clock signal, and outputs a control signal corresponding to frequencies of the first clock signal and the second clock signal. The input/output data pipeline circuit includes a first transmitting unit, which performs a transmission operation between the memory cell core and the input/output driver in response to activation of a first switching signal, and a second switching signal and a second transmitting unit which performs a transmission operation between the memory cell core and the input/output driver in response to activation of the control signal, and the first transmitting unit and the second transmitting unit are alternatively activated.
Preferably, the control signal generating unit detects a phase difference between the first clock signal and the second clock signal, and outputs the control signal with a logic state based on a detected result.
According to yet another aspect of the present invention, there is provided a semiconductor memory device. The semiconductor memory device comprises a memory cell core, an input/output driver, a control signal generating unit, and an input/output data pipeline circuit. The memory cell core includes a plurality of memory cells. The control signal generating unit receives a first clock signal, a second clock signal, and information about operation modes of the semiconductor memory device, and outputs a first switching signal, a second switching signal, and a control signal corresponding to the first clock signal, the second clock signal, and information about the operation modes of the semiconductor memory device. The input/output data pipeline circuit is connected to the memory cell core and the input/output driver, and transmits data stored in the memory cell core to the input/output driver in response to activation of the first switching signal, the second switching signal, and the control signal. The input/output data pipeline circuit includes a first transmitting unit, which is activated in response to activation of the first switching signal and the second switching signal, and a second transmitting unit, which is activated in response to activation of the control signal, and the first transmitting unit and the second transmitting unit are alternatively activated.